module Detector2 (
input Sin, CP, nCR,//声明输入
output reg Out//声明输出
);
reg [1:0] Current_state, Next_state;//声明状态触发器变量
parameter S0=2'b00, S1=2'b01, S2=2'b10, S3=2'b11;
//时序逻辑： 描述状态转换
always @(posedge CP, negedge nCR)
begin
if (~nCR) Current_state<=S0;//异步清零
else
Current_state<=Next_state;//在CP上升沿触发器状态翻转
end
//组合逻辑：描述下一状态和输出
always @(Current_state, Sin)
begin
     Out=1'b 0;
     Next_state=2'bxx;
     case(Current_state)
     S0: begin Out=1'b0; Next_state=(Sin==1)? S0 : S1; end
     S1: begin Out=1'b0; Next_state=(Sin==1)? S2 : S1;end
     S2: begin Out=1'b0; Next_state=(Sin==1)? S0 : S3; end
     S3: if (Sin==1)
     begin Out=1'b1; Next_state=S2; end
     else
     begin Out =1'b0; Next_state=S1; end
     endcase
end
endmodule
